1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device which has a structure of a memory cell array capable of simultaneously handling many I/O data, and can efficiently execute redundant repair when a failure occurs in a memory cell.
2. Description of the Background Art
In accordance with development of information communications technology in recent years, it has been demanded to provide semiconductor memory devices which have increased memory capacities, and further can perform fast and parallel handling of many data. As a typical example, these features are required in the case when the device is used for data processing of image data.
For satisfying the above demand, semiconductor memory devices having a so-called multi-bank and multi-I/O line structure have been increasingly used. The above structure of the semiconductor memory device has a plurality of banks each allowing independent reading and writing, and is provided with a large number of parallel I/O lines for allowing simultaneous handling of large volumes of data.
In the semiconductor memory device having a large-scaled memory cell array, it is important to employ an appropriate redundant repair technique for ensuring intended yields of products. According to the redundant repair technique, a defect in memory cells which occurred during manufacturing is repaired by a spare memory cell in a redundant circuit which is already prepared on the same chip.
With increase in memory capacity, it is desired or required to perform the redundant repair efficiently. For example, Japanese Patent Laying-Open No. 8-8344 has disclosed a technique of shift redundancy, in which redundant repair is performed a data line at a time by successively shifting the connections between the data lines. This prior technique will be referred to as a xe2x80x9cprior art 1xe2x80x9d hereinafter.
In addition, Japanese Patent Laying-Open No. 8-77793 has disclosed a technique, which will be referred to as a xe2x80x9cprior art 2xe2x80x9d hereinafter. In this prior art 2, a plurality of memory cell arrays (corresponding to banks), each of which allows read/write of data independently of the other memory cell arrays, commonly use a redundant circuit so that an efficient layout design can be performed.
However, the foregoing prior arts 1 and 2 would cause a problem if they were applied to the semiconductor memory device having the foregoing multi-bank and multi-I/O line structure without modification or change.
In the prior art 1, replacement of memory cells with spare cells is not performed a row at a time or a column at a time, but is performed by shifting the form of connection, which is made between data lines in the position including the defective memory cell. However, the setting for shifting the connection between data lines is designated in a fixed manner based on address program information, which is stored in advance in fuse elements or the like. Accordingly, if this prior art is applied to the multi-bank structure, the enormous number of fuse elements are required. The fuse element has a relatively large area, and therefore is not suitable to high-density integration. Thus, the fuse elements significantly affect the layout design.
According to the prior art 2, the units (banks) in the memory cell array, each of which can perform the read/write operations independently of the others, commonly use the same redundant circuit. According to this structure, it is necessary for input/output of data to provide switch circuits which can transmit data between respective data I/O lines and the redundant circuit. In the multi-bank and multi-I/O line structure, the required switch circuits are extremely large in number, and therefore the redundant repair circuit requires an extremely large area.
An object of the invention is to provide a structure of a semiconductor memory device having a structure of a memory cell array, which is provided with a large number of banks and a large number of data I/O lines and allows simultaneously handling of large volumes of data, and also having a redundant repair circuit which can efficiently perform redundant repair when a defect occurs in a memory cell.
In summary, the invention provides a semiconductor memory device for reading or writing storage data in accordance with a row address signal and a column address signal, including a memory cell array, a plurality of redundant row circuits, a third number of data buses, a plurality of data I/O lines, a redundant row control circuit and a data line connection switch circuit.
The memory cell array has normal memory cells arranged in rows and columns, and is divided into memory cell blocks arranged in a first number of rows and a second number of columns.
Each of the redundant row circuits is provided commonly to the first number of memory cell blocks neighboring in the column direction, and include spare storage elements arranged in rows and columns.
The third number of data buses are provided commonly to the respective memory cell blocks for transmitting the storage data to be read or written.
The plurality of data I/O lines are provided for transmitting the storage data, and include the third number of normal data I/O lines provided commonly to the first number of memory cell blocks neighboring to each other in the column direction. Each of the normal data I/O lines is provided for a fourth number of columns of the normal memory cells, and a plurality of spare row data I/O lines provided corresponding to the normal data I/O lines, respectively, and each provided for the fourth number of columns of the spare storage elements.
The redundant row control circuit instructs a redundant repair operation when the row address signal matches with at least one of defective row addresses in the normal memory cells.
The data line connection switch circuit is controlled by the redundant row control circuit, and selects one line from each set of the normal I/O line and the spare row data I/O line for connecting the selected lines to the corresponding data buses, respectively.
According to another aspect of the invention, the invention provides a semiconductor memory device for reading or writing storage data in accordance with a row address signal and a column address signal, including a memory cell array, a plurality of redundant column circuits, a third number of data buses, a plurality of data I/O lines, a redundant column control circuit and a data line connection switch circuit.
The memory cell array has normal memory cells arranged in rows and columns, and is divided into memory cell blocks arranged in a first number of columns and a second number of columns.
Each of the redundant column circuits is provided commonly to the second number of memory cell blocks neighboring in the row direction, and includes spare memory cells arranged in rows and columns.
The third number of data buses are provided commonly to the respective memory cell blocks for transmitting the storage data to be read or written.
The plurality of data I/O lines are provided for transmitting the storage data, and include the third number of normal data I/O lines provided commonly to the first number of memory cell blocks neighboring to each other in the column direction. Each of the normal data I/O lines is provided for a fourth number of columns of the normal memory cells, and spare column data I/O lines each arranged for the fourth number of spare memory cells.
The redundant column control circuit instructs a redundant repair operation when the column address signal matches with at least one of defective column addresses in the normal memory cells.
The data line connection circuit connects the third number of normal data I/O lines to the third number of data buses in the normal operation, respectively, and is controlled by the redundant column control circuit to connect the third number of data I/O lines selected from the normal data I/O lines and the spare column data lines to the third number of data buses, respectively, in said redundant repair operation.
According to still another aspect of the invention, a semiconductor memory device for reading and writing storage data in accordance with a row address signal and a column address signal, includes a memory cell array, a plurality of redundant row circuits, a plurality of redundant column circuits, a third number of data buses, a plurality of data I/O lines, a redundant row control circuit, a redundant column control circuit, a first data line connection switch circuit and a second data line connection circuit.
The memory cell array has normal memory cells arranged in rows and columns, and is divided into memory cell blocks arranged in a first number of rows and a second number of columns.
Each of the redundant row circuits is provided commonly to the first number of memory cell blocks neighboring in the column direction, and includes spare storage elements arranged in rows and columns.
Each of the redundant column circuits is provided commonly to the second number of memory cell blocks neighboring in the row direction, and includes spare memory cells arranged in rows and columns.
The third number of data buses are provided commonly to the respective memory cell blocks for transmitting the storage data to be read or written.
The plurality of data I/O lines are provided for transmitting the storage data, and include a third number of normal data I/O lines provided commonly to the first number of memory cell blocks neighboring to each other in the column direction. Each of the normal data I/O lines is arranged for the fourth number of columns of the normal memory cells, and a plurality of spare row data I/O lines corresponding to the third number of normal data I/O lines, respectively, and each arranged for the fourth number of columns of the spare storage elements, and spare column data I/O lines each arranged for the fourth number of columns of the spare memory cells.
The redundant row control circuit issues a row replacement instructing signal when the column address signal matches with at least one of defective row addresses in the plurality of predetermined normal memory cells.
The redundant column control circuit issues a data line shift control signal for instructing redundant repair operation when the column address signals matches with at least one of the defective column addresses in the plurality of preset normal memory cells.
The first data line connection switch circuit selects one from each set of the normal data I/O line and the spare row data I/O line in accordance with the row replacement instructing signals.
The second data line connection circuit selectively connects the third number of data I/O lines among the third number of normal data I/O lines selected by the first data line connection switch circuit and the spare column data I/O lines to the third number of data I/O buses in accordance with the data line shift control signals, respectively.
Accordingly, a major advantage of the invention is that the redundant row circuit is commonly used by the plurality of memory cell blocks, and the data I/O lines are arranged independently so that the layout design of the redundant row circuit can be performed efficiently, and the data read/write operations can be performed fast.
The redundant column circuit is commonly used by the plurality of memory cell blocks, and the data I/O lines are arranged independently for executing the redundant repair a data line at a time. Thereby, the layout design of the redundant column circuit can be performed efficiently, and the data read/write operations can be performed fast.
Further, both the redundant row circuit and the redundant column circuit are commonly used by the plurality of memory cell blocks, and the data I/O lines are arranged independently for executing the redundant column repair a data line at a time. Thereby, the layout design of the redundant circuit can be performed efficiently, and the data read/write operations can be performed fast.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.